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ds07-12532-2e fujitsu semiconductor data sheet 8-bit proprietary microcontroller cmos f 2 mc-8l mb89660r series mb89663r/665r/p665/w665 n outline the mb89660r series has been developed as a general-purpose version of the f 2 mc*-8l family consisting of proprietary 8-bit single-chip microcontrollers. in addition to a compact instruction set, the microcontrollers contain a great variety of peripheral functions such as timers, a uart, a serial interface, an 8-bit a/d converter, an input capture, an output compare, and an external interrupt. the mb89660r series is applicable to a wide range of applications from consumer products to industrial equipment. *: f 2 mc stands for fujitsu flexible microcontroller. n features ? packages qfp-64 sh-dip-64 ?f 2 mc-8l family cpu core (continued) n pac k ag e multiplication and division instructions 16-bit arithmetic operations test and branch instructions bit manipulation instructions, etc. instruction set optimized for controllers 64-pin plastic sh-dip 64-pin plastic qfp 64-pin ceramic sh-dip (dip-64p-m01) (dip-64c-a06) (fpt-64p-m06)
2 mb89660r series (continued) ? four types of timers 8-bit pwm timer 8/16-bit timer/counter 20-bit timebase timer ? functions that permit communications with a variety of devices uart which permits selection of synchronous/asynchronous communications a serial interface that permits selection of the transfer direction ? 8-bit a/d converter: 8 channels sense function capable of performing voltage compare operation in 5 m s at 10 mhz started by external input possible ? real-time control input capture: 2 channels output compare: 2 channels ? external interrupt: 4 channels four channels are independent and capable of wake-up from low-power consumption modes (with an edge detection function). ? low power consumption (standby modes) stop mode (oscillation stops to minimize the current consumption.) sleep mode (the cpu stops to reduce the current consumption to approx. 1/3 of normal.) hardware standby mode (wake-up from this mode and activation by pin input only.)
3 mb89660r series n product lineup (continued) mb89665r mb89w665 mb89p665 classification mass-produced products (mask rom products) eprom product one-time prom product, also used for evaluation rom size 8 k 8 bits (internal mask rom) 16 k 8 bits (internal mask rom) 16 k 8 bits (internal prom, to be programmed with general-purpose eprom programmer) ram size 256 8 bits 512 8 bits cpu functions the number of instructions: 136 instruction bit length: 8 bits instruction length: 1 to 3 bytes data bit length: 1,8, 16 bits minimum execution time: 0.4 m s at 10 mhz interrupt processing time: 3.6 m s at 10 mhz ports output ports (cmos): 8 output ports (n-ch open-drain): 8 (all also serve as peripherals.) general-purpose i/o ports (cmos): 36 (19 ports also serve as peripherals.) to t a l : 5 2 8-bit pwm timer 8-bit interval timer operation (square wave output capable, operating clock cycle: 0.4 m s to 25.6 m s) 8-bit resolution pwm operation (conversion cycle: 102 m s to 6.6 ms) 8/16-bit timer/ counter 2-channel 8-bit timer/counter operation (timer 1 and timer 2, each operating clock independence, square wave output capable), or 16-bit timer/counter operation (operating clock cycle: 0.8 m s to 12.8 m s) in timer 1 or 16-bit timer/counter operation, event counter operation by external clock input uart variable data length (6-, 7-, 8-bit length), built-in baud rate generator, error detection function, built-in full-duplex double buffer nrz type transfer format, clk synchronous/asynchronous data transfer capable transfer rate setting by dedicated band rate generator, external clock, 8-bit pwm timer 8-bit serial i/o 8 bits lsb/msb first selectable one clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 0.8 m s, 3.2 m s, 12.8 m s) 8-bit a/d converter 8-bit resolution 8 channels a/d conversion function (conversion time: 18 m s at 10 mhz) sense function (conversion time: 5 m s at 10 mhz) capable of continuous activation by an external clock or an internal clock reference voltage input real-time i/o 16-bit timer: operating clock cycle (0.4 m s, 0.8 m s, 1.6 m s, 3.2 m s) overflow interrupt input capture: 16 bits 2 channels (external trigger edge selectable) output capture: 16 bits 2 channels mb89663r item part number
4 mb89660r series (continued) * : varies with conditions such as the operating frequency. (see section n electrical characteristics.) n package and corresponding products : available : not available note: for more information about each package, see section n package dimensions. mb89665r mb89w665 mb89p665 external interrupt 4 channels (source flag, enable flag independently) rising edge/falling edge/both edges selectable used also for wake-up from stop/sleep mode. (edge detection is also permitted in stop mode.) (wake-up from hardware standby mode is not possible) low-power consumption (standby modes) sleep mode, stop mode, and hardware standby mode process cmos operating voltage* (when using a/d converter) 2.2 v to 6.0 v (3.5 v to 6.0 v) 2.7 v to 6.0 v (3.5 v to 6.0 v) package mb89663r mb89665r mb89p665 mb89w665 dip-64p-m01 fpt-64p-m06 dip-64c-a06 mb89663r item part number
5 mb89660r series n differences among products 1. memory size before evaluating using the otprom (one-time prom) product (also used for evaluation), verify its differences from the product that will actually be used: take particular care on the following points: ? on the mb89663r, register bank from 16 to 32 cannot be used. ? on the mb89p665, address bff0 h to bff6 h comprise the option setting area, option settings can be read by reading these addresses. ? the stack area, etc., is used. 2. current consumption ? when operated at low speed, the product with an otprom or an eprom will consume more current than the product with a mask rom. ? however, the same is the current comsumption in sleep/stop modes. (for more information, see sections n electrical characteristics and n example characteristics. 3. mask options functions that can be selected as options and how to designate these options vary with product. before using options, check section n mask options. take particular care on the following points: ? on the mb89p665, a pull-up resistor must be selected in a group of four pins for p54 to p57. ? for all products, p50 to p57 must be set for no pull-up resistor optional when an a/d converter is used. 4. differences between the mb89660 and mb89660r series ? memory access area memory access area of both the mb89660r and mb89660 series is the same. ? other specifications for mb89660r series, input level at p00 to p07 and p10 to p17 is fixed when the hardware is standing-by. and for mb89660 series, input level at p00 to p07 and p10 to p17 is not fixed. therefore, when the medium voltage is input there such as input open, the standby current will increase. ? electrical specifications/electrical characteristics there are differences at pull down resistances of mod0 and mod1 between mb89660r series and mb89660 series. for more information, see 3. dc characteristics in section n electrical characteristics. electrical specification of the other items of mb89660r series and mb89660 series are equivalent. however, it is possible that the valid characteristic will be modified. see the corresponding characteristic respectively for detail.
6 mb89660r series n pin assignment (dip-64p-m01) (dip-64c-a06) (top view) 1 p36/rto1 2 p37/adst 3 p40/sck1 4 p41/so1 5 p42/si1 6 p43/sck2 7 p44/so2 8 p45/si2 9 p46/pto 10 p47 11 p50/an0 12 p51/an1 13 p52/an2 14 p53/an3 15 p54/an4 16 p55/an5 17 p56/an6 18 p57/an7 19 av cc 20 avr 21 av ss 22 p60/int0 23 p61/int1 24 p62/int2 25 p63/int3 26 hst 27 rst 28 mod0 29 mod1 30 x0 31 x1 32 v ss v cc 64 p35/rto0 63 p34/rti1 62 p33/rti0 61 p32/to2 60 p31/to1 59 p30/ec 58 v ss 57 p00 56 p01 55 p02 54 p03 53 p04 52 p05 51 p06 50 p07 49 p10 48 p11 47 p12 46 p13 45 p14 44 p15 43 p16 42 p17 41 p20 40 p21 39 p22 38 p23 37 p24 36 p25 35 p26 34 p27 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 p45/si2 p46/pto p47 p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 av cc avr av ss p60/int0 p61/int1 p62/int2 p63/int3 hst 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p30/ec v ss p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 p20 64 63 62 61 60 59 58 57 56 55 54 53 52 p44/so2 p43/sck2 p42/si1 p41/so1 p40/sck1 p37/adst p36/rto1 v cc p35/rto0 p34/rti1 p33/rti0 p32/to2 p31/to1 20 21 22 23 24 25 26 27 28 29 30 31 32 rst mod0 mod1 x0 x1 v ss p27 p26 p25 p24 p23 p22 p21 (fpt-64p-m06) (top view)
7 mb89660r series n pin description (continued) *1: dip-64p-m01, dip-64c-a06 *2: fpt-64p-m06 pin no. pin name circuit type function sh-dip *1 qfp *2 30 23 x0 a crystal oscillator pins 31 24 x1 28 21 mod0 b operation mode select pins connect directly to v cc or v ss . a pull-down resistor is selectable as an option for mask rom products. 29 22 mod1 27 20 rst c reset i/o pin this port is an n-ch open-drain output type with pull-up resistor and of hysteresis input type. l is output from this pin by an internal reset source. the internal circuit is initialized by the input of l. 26 19 hst g hardware standby input pin connect directly to v cc when hardware standby is not used. 56 to 49 49 to 42 p00 to p07 d general-purpose i/o ports 48 to 41 41 to 34 p10 to p17 40 to 33 33 to 26 p20 to p27 f general-purpose output ports 58 51 p30/ec e general-purpose i/o port also serves as an external clock input for an 8/16-bit timer/counter. this pin is of hysteresis input type and with a noise canceller. 59 52 p31/to1 e general-purpose high-current i/o port also serves as an 8/16-bit timer/counter output. this pin is of hysteresis input type and with a noise canceller. 60 53 p32/to2 e general-purpose i/o port also serves as an 8/16-bit timer/counter output. this pin is of hysteresis input type and with a noise canceller. 61 54 p33/rti0 e general-purpose i/o ports also serve as the data input for the input capture. this pin is of hysteresis input type and with a noise canceller. 62 55 p34/rti1 63 56 p35/rto0 e general-purpose i/o ports also serve as the data output for the output compare. this pin is of hysteresis input type and with a noise canceller. 158p36/rto1 2 59 p37/adst e general-purpose high-current i/o port also serves as the external starting input for the a/d converter. this pin is of hysteresis input type and with a noise canceller.
8 mb89660r series (continued) *1: dip-64p-m01, dip-64c-a06 *2: fpt-64p-m06 pin no. pin name circuit type function sh-dip *1 qfp *2 3 60 p40/sck1 e general-purpose i/o port also serves as the clock i/o for the uart. this pin is of hysteresis input type and with a noise canceller. 4 61 p41/so1 e general-purpose i/o port also serves as the data output for the uart. this pin is of hysteresis input type and with a noise canceller. 5 62 p42/si1 e general-purpose i/o port also serves as the data input for the uart. this pin is of hysteresis input type and with a noise canceller. 6 63 p43/sck2 e general-purpose i/o port also serves as the clock i/o for the 8-bit serial i/o interface. this pin is of hysteresis input type and with a noise canceller. 7 64 p44/so2 e general-purpose i/o port also serves as the data output for the 8-bit serial i/o interface. this pin is of hysteresis input type and with a noise canceller. 8 1 p45/si2 e general-purpose i/o port also serves as the data input for the 8-bit serial i/o interface. this pin is of hysteresis input type and with a noise canceller. 9 2 p46/pto e general-purpose i/o port also serves as a toggle output for an 8-bit pwm timer. this pin is of hysteresis input type and with a noise canceller. 10 3 p47 e general-purpose i/o port this pin is of hysteresis input type and with a noise canceller. 11 to 18 4 to 11 p50/an0 to p57/an7 h n-ch open-drain output ports also serve as the analog input for the a/d converter. 22 to 25 15 to 18 p60/int0 to p63/int3 e general-purpose i/o ports these pins also serve as an external interrupt input. these pins are of hysteresis input type and with a noise canceller. 64 57 v cc power supply pin 32 57 25 50 v ss power supply (gnd) pins 19 12 av cc a/d converter power supply pin 20 13 avr a/d converter reference voltage input pin 21 14 av ss a/d converter power supply pin use this pin at the same voltage as v ss .
9 mb89660r series n i/o circuit type (continued) type circuit remarks a ? oscillation feedback resistor of approximately 1 m w at 5.0 v b ? cmos input ? built-in pull-down resistor (mask rom products only) c ? output pull-up resistor (p-ch) of approximately 50 k w at 5.0 v ? hysteresis input d ? cmos output ? cmos input ? pull-up resistor option of approximately 50 k w at 5.0 v e ? cmos output ? hysteresis input ? pull-up resistor option of approximately 50 k w at 5.0 v f ? cmos output x1 x0 standby control signal n-ch p-ch p-ch n-ch n-ch r p-ch n-ch p-ch n-ch p-ch r p-ch n-ch p-ch r p-ch n-ch
10 mb89660r series (continued) type circuit remarks g ? hysteresis input h ? n-ch open-drain output ? analog input ? pull-up resistor option of approximately 50 k w at 5.0 v p-ch n-ch p-ch r analog input
11 mb89660r series n handling devices 1. preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on 1. absolute maximum ratings in section n electrical characteristics is applied between v cc and v ss . when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. also take care to prevent the analog power supply (av cc and avr) and analog input from exceeding the digital power supply (v cc ) when the analog system power supply is turned on and off. 2. treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistor. 3. treatment of power supply pins on microcontrollers with a/d converters connect to be av cc = v cc and av ss = avr = v ss if the a/d converters are not in use. 4. power supply voltage fluctuations although operation is assured within the rated range of v cc power supply voltage, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. stabilizing voltage supplied to the ic is therefore important. as stabilization guidelines, it is recommended to control power so that v cc ripple fluctuations (p-p value) will be less than 10% of the standard v cc value at the commercial frequency(50 to 60 hz) and the transient fluctuation rate will be less than 0.1 v/ms at the time of a momentary fluctuation such as when power is switched. 5. precautions when using an external clock when an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and wake-up from stop mode.
12 mb89660r series n programming to the eprom on the mb89p665 the mb89p665 is an otprom version of the mb89660r series. 1. features ? 16-kbyte prom on chip ? options can be set using the eprom programmer. ? equivalency to the mbm27c256a in eprom mode (when programmed with the eprom programmer) 2. memory space memory space in each mode such as 16-kbyte prom, option area is diagrammed below. 0000 h 0080 h 0280 h bff0 h bff7 h c000 h ffff h single chip i/o ram not available not available not availble prom 16 kb 0000 h 3ff0 h 3ff7 h 4000 h 7fff h eprom mode (corresponding addresses on the eprom programmer) option area eprom 16 kb vacancy (read value ff h ) vacancy (read value ff h ) address
13 mb89660r series 3. programming to the prom in eprom mode, the mb89p665a functions equivalent to the mbm27c256a. this allows the prom to be programmed with a general-purpose eprom programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. programming procedure (1) set the eprom programmer to the mbm27c256a. (2) load program data into the eprom programmer at 4000 h to 7fff h (note that addresses c000 h to ffff h while operating as a single chip correspond to 4000 h to 7fff h in eprom mode). load option data into addresses 3ff0 h to 3ff6 h of the eprom programmer. (for information about each corresponding option, see 8. setting otprom options.) (3) program with the eprom programmer. 4. recommended screening conditions high-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked otprom microcomputer program. program, verify aging +150 c, 48 hrs. data verification assembly
14 mb89660r series 5. programming yield due to its nature, bit programming test cant be conducted as fujitsu delivery test. for this reason, a programming yield of 100% cannot be assured at all times. 6. erasure procedure in order to clear all locations of their programmed contents, it is necessary to expose the internal eprom to an ultraviolet light source. a dosage of 10 w-seconds/cm 2 is required to completely erase an internal eprom. this dosage can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 angstroms (?)) with intensity of 12000 m w/cm 2 for 15 to 21 minuites. the internal eprom should be about one inch from the source and all filters should be removed from the uv light source prior to erasure. it is important to note that the internal eprom and similar devices, will erase with light sources having wave- lengths shorter than 4000 ?. although erasure time will be much longer than with uv source at 2537 ?, nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal eprom, and exposure to them should be prevented to realize maximum system reliability. if used in such an environment, the package windows should be covered by an opaque label or substance. 7. eprom programmer socket adapter and recommended programmer manufacturer inquiry: sun hayato co., ltd.: tel: (81)-3-3986-0403 fax: (81)-3-5396-9106 minato electronics inc.: tel: usa (1)-916-348-6066 japan (81)-45-591-5611 data i/o co., ltd.:tel: usa/asia (1)-206-881-6444 europe (49)-8-985-8580 note: connect the adapter jumper pin to v ss when using. part number package compatible socket adapter sun hayato co., ltd. recommended programmer manufacturer and programmer name minato electronics inc. data i/o co., ltd. 1890a 1891 1930 r4945a mb89w665 sh-dip-64 rom-64qf-28dp-8l5 mb89p665pf qfp-64 rom-64qf-28dp-8l recommended recommended mb89p665 sh-dip-64 rom-64sd-28dp-8l
15 mb89660r series 8. setting otprom options the programming procedure is the same as that for the prom. options can be set by programming values at the addresses shown on the memory map. the relationship between bits and options is shown on the following bit map: ? otprom option bit map note: ? each bit is set to 1 as the initialized value, therefore the pull-up option is not selected. ? do not write 0 to the vacant bit. the read value of the vacant bit is 1, unless 0 is written to it. address bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 3ff0 h vacancy readable and writable vacancy readable and writable vacancy readable and writable oscillation stabilization time 1: crystal 0: ceramic reset pin output 1: yes 0: no power-on reset 1: yes 0: no vacancy readable and writable vacancy readable and writable 3ff1 h p07 pull-up 1: no 1: yes p06 pull-up 1: no 1: yes p05 pull-up 1: no 0: yes p04 pull-up 1: no 0: yes p03 pull-up 1: no 0: yes p02 pull-up 1: no 0: yes p01 pull-up 1: no 0: yes p00 pull-up 1: no 0: yes 3ff2 h p17 pull-up 1: no 0: yes p16 pull-up 1: no 0: yes p15 pull-up 1: no 0: yes p14 pull-up 1: no 0: yes p13 pull-up 1: no 0: yes p12 pull-up 1: no 0: yes p11 pull-up 1: no 0: yes p10 pull-up 1: no 0: yes 3ff3 h p37 pull-up 1: no 0: yes p36 pull-up 1: no 0: yes p35 pull-up 1: no 0: yes p34 pull-up 1: no 0: yes p33 pull-up 1: no 0: yes p32 pull-up 1: no 0: yes p31 pull-up 1: no 0: yes p30 pull-up 1: no 0: yes 3ff4 h p47 pull-up 1: no 0: yes p46 pull-up 1: no 0: yes p45 pull-up 1: no 0: yes p44 pull-up 1: no 0: yes p43 pull-up 1: no 0: yes p42 pull-up 1: no 0: yes p41 pull-up 1: no 0: yes p40 pull-up 1: no 0: yes 3ff5 h vacancy readable and writable vacancy readable and writable vacancy readable and writable p57 to p54 pull-up 1: no 0: yes p53 pull-up 1: no 0: yes p52 pull-up 1: no 0: yes p51 pull-up 1: no 0: yes p50 pull-up 1: no 0: yes 3ff6 h vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable p63 pull-up 1: no 0: yes p62 pull-up 1: no 0: yes p61 pull-up 1: no 0: yes p60 pull-up 1: no 0: yes
16 mb89660r series n block diagram x0 x1 oscillator rst clock controller reset circuit (wdt) 8 8 p00 to p07 p10 to p17 cmos i/o port cmos output port ram f 2 mc-8l cpu rom 21-bit timebase timer 8-bit pwm timer uart port 4 cmos i/o port n-ch open-drain output port 8-bit a/d converter 4 4 external interrupt cmos i/o port p60/int0 to p63/int3 8 avr av cc av ss 8 p50/an0 to p57/an7 p44/so2 p45/si2 p46/pto internal bus hst hardware standby v cc , v ss 2 mod0, mod1 the other pins p47 8-bit serial i/o p43/sck2 p41/so1 p42/si1 p40/sck1 p35/rto0 p36/rto1 output compare cmos i/o port 16-bit timer input capture p33/rti0 p34/rti1 p31/to1 p32/to2 p30/ec 8/16-bit timer/counter real-time i/o p37/adst port 0 and 1 port 3 port 2 port 5 port 6 8 p20 to p27
17 mb89660r series n cpu core 1. memory space the microcontrollers of the mb89660r series offer 64 kbytes of memory for storing all of i/o, data, and program areas. the i/o area is allocated from the lowest address. the data area is allocated immediately above the i/o area. the data area can be divided into register, stack, and direct areas according to the application. the program area is allocated from exactly the opposite end, that is, near the highest address. the tables of interrupt reset vectors and vector call instructions are allocated from the highest address within the program area. the memory space of the mb89660r series is structured as illustrated below. memory space 0000 h 0080 h 0100 h 0180 h e000 h ffff h mb89663r i/o ram 256 b register 0000 h 0080 h 0100 h 0200 h c000 h ffff h mb89665r mb89w665 mb89p665 i/o ram 512 b register rom* 16 kb not available not available 0280 h *: when the mb89p665 is used for evaluation, the internal rom cannot be used. rom 8 kb
18 mb89660r series 2. registers the f 2 mc-8l family has two types of registers; dedicated hardware registers in the cpu and general-purpose memory registers. the following dedicated registers are provided: program counter (pc): a 16-bit register for indicating the instruction storage positions accumulator (a): a 16-bit temporary register for storing arithmetic operations, etc. when the instruction is an 8-bit data processing instruction, the lower byte is used. temporary accumulator (t): a 16-bit register which is used for arithmetic operations with the accumulator when the instruction is an 8-bit data processing instruction, the lower byte is used. index register (ix): a 16-bit register for index modification extra pointer (ep): a 16-bit pointer for indicating a memory address stack pointer (sp): a 16-bit pointer for indicating a stack area program status (ps): a 16-bit register for storing a register pointer, a condition code the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and the lower 8 bits for use as a condition code register (ccr). (see the diagram below.) pc a t ix ep sp ps 16 bits : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status fffd h indeterminate indeterminate indeterminate indeterminate indeterminate i-flag = 0, il1, 0 = 11 the other bit values are indeterminate. initial value structure of the program status register vacancy h i il1, 0 n z vc 54 rp ps 109876 3210 15 14 13 12 11 rp ccr vacancy vacancy
19 mb89660r series the rp indicates the address of the register bank currently in use. the relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. the ccr consists of bits indicating the results of arithmetic operations and the contents of transfer data, and bits for control of cpu operations at the time of an interrupt. h-flag: set to 1 when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. cleared to 0 otherwise. this flag is for decimal adjustment instructions. i-flag: interrupt is enabled when this flag is set to 1. interrupt is disabled when the flag is cleared to 0. cleared to 0 at the reset. il1, 0: indicates the level of the interrupt currently allowed. processes an interrupt only if its request level is higher than the value indicated by this bit. n-flag: set to 1 if the msb becomes 1 as the result of an arithmetic operation. cleared to 0 otherwise. z-flag: set to 1 when an arithmetic operation results in 0. cleared to 0 otherwise. v-flag: set to 1 if the complement on 2 overflows as a result of an arithmetic operation. cleared to 0 if the overflow does not occur. c-flag: set to 1 when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared to 0 otherwise. set to the shift-out value in the case of a shift instruction. il1 il0 interrupt level high-low 00 1 high low 01 10 2 11 3 rule for conversion of actual addresses of the general-purpose register area ? a15 ? a14 ? a13 ? a12 ? a11 ? a10 ? a9 ? a8 r4 a7 r3 a6 r2 a5 r1 a4 r0 a3 b2 a2 b1 a1 b0 a0 lower op codes rp generated addresses
20 mb89660r series the following general-purpose registers are provided: general-purpose registers: an 8-bit register for storing data the general-purpose registers are of 8 bits and located in the register banks of the memory. one bank contains eight registers. up to a total of 16 banks can be used on the mb89663r and a total of 32 banks can be used on the mb89665r/p665/w665. the bank currently in use is indicated by the register bank pointer (rp). note: the number of register banks that can be used varies with the ram size. r1 r2 r3 r4 r5 r6 r7 this address = 0100 h + 8 (rp) memory area 32 banks r0 register bank configuration
21 mb89660r series n i/o map (continued) address read/write register name register description 00 h (r/w) pdr0 port 0 data register 01 h (w) ddr0 port 0 data direction register 02 h (r/w) pdr1 port 1 data register 03 h (w) ddr1 port 1 data direction register 04 h (r/w) pdr2 port 2 data register 05 h vacancy 06 h vacancy 07 h vacancy 08 h (r/w) stbc standby control register 09 h (r/w) wdtc watchdog timer control register 0a h (r/w) tbtc timebase timer control register 0b h vacancy 0c h (r/w) pdr3 port 3 data register 0d h (w) ddr3 port 3 data direction register 0e h (r/w) pdr4 port 4 data register 0f h (w) ddr4 port 4 data direction register 10 h (r/w) pdr5 port 5 data register 11 h vacancy 12 h (r/w) pdr6 port 6 data register 13 h (w) ddr6 port 6 data direction register 14 h vacancy 15 h (r/w) adc1 a/d converter control register 1 16 h (r/w) adc2 a/d converter control register 2 17 h (r/w) adcd a/d converter data register 18 h (r/w) t2cr timer 2 control register 19 h (r/w) t1cr timer 1 control register 1a h (r/w) t2dr timer 2 data register 1b h (r/w) t1dr timer 1 data register 1c h (r/w) cntr pwm control register 1d h (w) comr pwm compare register 1e h vacancy 1f h vacancy
22 mb89660r series (continued) note: do not use vacancies. address read/write register name register description 20 h (r/w) smc uart serial mode control register 21 h (r/w) src uart serial rate control register 22 h (r/w) ssd uart serial status/data register 23 h (r/w) sidr/sodr uart serial data register 24 h (r/w) smr serial mode register 25 h (r/w) sdr serial data register 26 h (r/w) eic1 external interrupt control register 1 27 h (r/w) eic2 external interrupt control register 2 28 h (r/w) tmcr timer control register 29 h (r) tchr timer count register (h) 2a h (r) tclr timer count register (l) 2b h (r/w) opcr output control register 2c h (r/w) cpr0h output compare register 0 (h) 2d h (r/w) cpr0l output compare register 0 (l) 2e h (r/w) cpr1h output compare register 1 (h) 2f h (r/w) cpr1l output compare register 1 (l) 30 h (r/w) iccr input capture control register 31 h (r/w) icic input capture interrupt control register 32 h (r) icr0h input capture register 0 (h) 33 h (r) icr0l input capture register 0 (l) 34 h (r) icr1h input capture register 1 (h) 35 h (r) icr1l input capture register 1 (l) 36 h vacancy 37 h vacancy 38 h vacancy 7c h (w) ilr1 interrupt level setting register 1 7d h (w) ilr2 interrupt level setting register 2 7e h (w) ilr3 interrupt level setting register 3 7f h vacancy
23 mb89660r series n electrical characteristics 1. absolute maximum ratings (av ss = v ss = 0.0 v) * : use av cc and v cc set to the same voltage. take care so that av cc does not exceed v cc , such as when power is turned on. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol value unit remarks min. max. power supply voltage v cc av cc v ss C 0.3 v ss + 7.0 v * avr v ss C 0.3 v ss + 7.0 v avr must not exceed av cc + 0.3 v input voltage v i v ss C 0.3 v cc + 0.3 v output voltage v o v ss C 0.3 v cc + 0.3 v l level maximum output current i ol 20ma l level average output current i olav 4ma average value (operating current operating rate) l level total maximum output current s i ol 100ma l level total average output current s i olav 40ma average value (operating current operating rate) h level maximum output current i oh C20ma h level average output current i ohav C4ma average value (operating current operating rate) h level total maximum output current s i oh C50ma h level total average output current s i ohav C20ma average value (operating current operating rate) power consumption p d 300mw operating temperature t a C40 +85 c storage temperature tstg C55 +150 c
24 mb89660r series 2. recommended operating conditions (av ss = v ss = 0.0 v) * : these values vary with the operating frequency and analog assurance range. see figure. 1 and 5. a/d converter electrical characteristics. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter sym- bol value unit remarks min. max. power supply voltage v cc av cc 2.2* 6.0* v normal operation assurance range* mb89663r/665r 2.7* 6.0* v normal operation assurance range* mb89p665 1.5 6.0 v retains the ram state in the stop mode avr 0.0 av cc v operating temperature t a C40 +85 c 1 2 3 4 5 6 110 operating voltage (v) 5 234 6789 analog accuracy assured in the av cc = v cc = 3.5 to 6.0 v range main clock operating frequency (mhz) note: the shaded area is assured only for the mb89663r/665r. operation assurance range figure 1 operating voltage vs. main clock operating frequency (mhz)
25 mb89660r series 3. dc characteristics (av cc = v cc = +5.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) (continued) parameter symbol pin name condition value unit remarks min. typ. max. h level input voltage v ih p00 to p07, p10 to p17 0.7 v cc v cc + 0.3 v v ihs rst , hst p30 to p37, p40 to p47, p60 to p63 0.8 v cc v cc + 0.3 v l level input voltage *1 v il p00 to p07, p10 to p17 v ss C 0.3 0.3 v cc v v ils rst , hst p30 to p37, p40 to p47, p60 to p63 v ss C 0.3 0.2 v cc v open-drain output pin applied voltage v d p50 to p57 v ss C 0.3 v cc + 0.3 v h level output voltage v oh1 p00 to p07, p10 to p17, p20 to p27, p30, p32 to p36, p40 to p47, p60 to p63 i oh = C2.0 ma 2.4 v v oh2 p31, p37 i oh = C15 ma 2.4 v l level output voltage v ol1 p00 to p07, p10 to p17, p20 to p27, p30, p32 to p36, p40 to p47, p50 to p57, p60 to p63 i ol = +1.8 ma 0.4v v ol2 p31, p37 i ol = +12 ma 0.4v v ol3 rst i ol = +4.0 ma 0.4v input leakage current (hi-z output leakage current) i li p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p60 to p63 0.45 v < v i < v cc 5 m a without pull-up resistor pull-up resistance r pulu rst , option select pin v i = 0.0 v 25 50 100 k w
26 mb89660r series (continued) (av cc = v cc = +5.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) *1: fix mod0 and mod1 to v ss . *2: the power supply current is measured on the external clock at v cc = 5.0 v. *3: for information on t inst , see (4) instruction cycle in 4. ac characteristics. parameter symbol pin name condition value unit remarks min. typ. max. pull-down resistance r puld mod0, mod1 v i = +5.0 ma 25 50 100 k w mask rom products only power supply current i cc v cc f c = 10 mhz t inst *3 = 0.4 m s in the normal mode 1518ma mb89663r/ 665r 1720ma mb89p665/ w665 i ccs f c = 10 mhz t inst *3 = 0.4 m s in the sleep mode 6 8ma i cch t a = +25 c t inst *3 = 0.4 m s in the stop mode 10 m a i a av cc f c = 10 mhz, when a/d conversion is operating 2.54.5ma i ah f c = 10 mhz, t a = +25 c, when a/d conversion is not operating 5 m a input capacitance c in other than av cc , av ss , v cc , and v ss f = 1 mhz 10 pf
27 mb89660r series 4. ac characteristics (1) reset timing, hardware standby timing (v cc = +5.0 v 10%, av ss =v ss = 0.0 v, t a = C40 c to +85 c) * : t xcyl is the oscillation cycle (1/f c ) to input to the x0 pin. (2) power-on reset (av ss = v ss = 0.0 v, t a = C40 c to +85 c) note: make sure that power supply rises within the oscillation stabilization time selected. if power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. parameter symbol condition value unit remarks min. max. rst l pulse width t zlzh 16 t xcyl ns hst l pulse width t hlhh 16 t xcyl ns parameter symbol condition values unit remarks min. max. power supply rising time t r 50ms power supply cut-off time t off 1ms due to repeated operations t zlzh 0.2 v cc 0.2 v cc rst t hlhh 0.2 v cc 0.2 v cc hst 0.2 v 0.2 v 2.0 v v cc 0.2 v t r t off
28 mb89660r series (3) clock timing (av ss = v ss = 0.0 v, t a = C40 c to +85 c) (4) instruction cycle parameter symbol pin name condition value unit remarks min. typ. max. clock frequency f c x0, x1 1 10 mhz clock cycle time t xcyl x0, x1 100 1000 ns input clock pulse width p wh p wl x0 20 ns external clock input clock rising/ falling time t cr t cf x0 10 ns external clock parameter symbol value (typical) unit remarks instruction cycle (minimum execution time) t inst 4/f c m s when operating at f c = 10 mhz 0.2 v cc 0.8 v cc x0 0.2 v cc t cr t cf 0.8 v cc 0.2 v cc x0 x1 x0 x1 when a crystal or ceramic resonator is used when an external clock is used open t xcyl p wh p wl x0 and x1 timing and conditions of applied voltage
29 mb89660r series (5) serial i/o timing and uart timing (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc sck1, sck2 internal shift clock mode 2 t inst * m s sck1 ? so1 time sck2 ? so2 time t slov sck1, so1 sck2, so2 C200 200 ns valid si1 ? sck1 - valid si1 ? sck1 - t ivsh si1, sck1 si2, sck2 1/2 t inst * m s sck1 - ? valid si1 hold time sck2 - ? valid si2 hold time t shix sck1, si1 sck2, si2 1/2 t inst * m s serial clock h pulse width t shsl sck1, sck2 external shift clock mode 1 t inst * m s serial clock l pulse width t slsh sck1, sck2 1 t inst * m s sck1 ? so1 time sck2 ? so2 time t slov sck1, so1 sck2, so2 0 200 ns valid si1 ? sck1 - valid si2 ? sck2 - t ivsh si1, sck1 si2, sck2 1/2 t inst * m s sck1 - ? valid si1 hold time sck2 - ? valid si2 hold time t shix sck1, si1 sck2, si2 1/2 t inst * m s
30 mb89660r series 0.8 v 2.4 v t scyc t slov 0.2 v cc t shix 0.8 v t ivsh 0.8 v cc 0.2 v cc 0.8 v cc sck1 so1 si1 sck2 so2 si2 2.4 v 0.8 v t slsh 2.4 v t slov 0.2 v cc t shix 0.8 v cc 0.8 v t ivsh 0.8 v cc 0.2 v cc 0.8 v cc sck1 so1 si1 sck2 so2 si2 t shsl 0.8 v cc 0.2 v cc 0.2 v cc serial i/o timing and uart timing (internal shift clock mode) serial i/o timing and uart timing (external shift clock mode)
31 mb89660r series (6) peripheral input timing (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol pin name condition value unit remarks min. max. peripheral input h level pulse width 1 t ilih1 rti0, rti1 int0 to int3 2 t inst * m s peripheral input l level pulse width 1 t ihil1 m s peripheral input h level pulse width 2 t ilih2 ec 1 t inst * m s peripheral input l level pulse width 2 t ihil2 m s peripheral input h level pulse width 3 t ilih3 adst a/d mode 32 t inst * m s peripheral input l level pulse width 3 t ihil3 m s peripheral input h level pulse width 3 t ilih3 sense mode 8 t inst * m s peripheral input l level pulse width 3 t ihil3 m s 0.2 v cc 0.8 v cc t ihil1 0.8 v cc int0 to 3 rti0, rti1 0.2 v cc t ilih1 0.2 v cc 0.8 v cc t ihil2 0.8 v cc ec 0.2 v cc t ilih2 0.2 v cc 0.8 v cc t ihil3 0.8 v cc adst 0.2 v cc t ilih3
32 mb89660r series (7) noise filter (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin condition value unit remarks min. max. noise filter width 1 t inf1 p30 to p37, p40 to p47, p60 to p63 during port operation 15 ns noise filter width 2 t inf2 p60 to p63 during external interrupt 60 ns t inf 1, 2 0.2 v cc t inf 1, 2 0.2 v cc input waveform 0.8 v cc 0.8 v cc
33 mb89660r series 5. a/d converter electrical characteristics (av cc = v cc = +3.5 v to 6.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle in 4. ac characteristics. 6. a/d glossary ? resolution analog changes that are identifiable by the a/d converter when the number of bits is 8, analog voltage can be divided into 2 8 = 256. ? linearity error (unit: lsb) the deviation of the straight line connecting the zero transition point (0000 0000 ? 0000 0001) with the full-scale transition point (1111 1111 ? 1111 1110) from actual conversion characteristics ? differential linearity error (unit: lsb) the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value ? total error (unit: lsb) the difference between theoretical and actual conversion values parameter symbol pin name condition value unit remarks min. typ. max. resolution 8bit total error avr = av cc 2.0 lsb linearity error 1.0 lsb differential linearity error 0.9 lsb zero transition voltage v ot av ss C 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb mv full-scale transition voltage v fst avr C 3.5 lsb avr C 1.5 lsb avr + 0.5 lsb mv interchannel disparity 1lsb a/d mode conversion time 44 t isnt * m s sense mode conversion time 12 t inst * m s analog port input circuit i ain an0 to an7 10 m a analog input voltage 0 avr v reference voltage avr 0av cc v reference voltage supply current i r avr = 5.0 v when a/d conversion is operating 150 m a i rh avr = 5.0 v when a/d conversion is not operating 5 m a
34 mb89660r series 7. a/d converter ? input impedance of analog input pins the a/d converter used for the mb89660r series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for eight instruction cycles after starting a/d conversion. for this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. therefore, it is recommended to keep the output impedance of the external circuit low (below 2 k w ). note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of approx. 0.1 m f for the analog input pin. ?error the smaller the | avr C av ss |, the greater the error would become relatively. v ot v nt v ( n+i )t v fst digital output (1 lsb n + v ot ) 0000 0000 0000 0000 0001 0010 1111 1111 1110 1111 1 lsb = avr 256 linearity error = v nt ?(1 lsb n + v ot ) 1 lsb differential linearity error = v ( n + 1 ) t ?v nt 1 lsb analo g input actual conversion value theoretical conversion value ?1 total error = 1 lsb v nt ?(1 lsb n + 1 lsb) linearity error closes for 8 instruction cycles after starting a/d conversion. sample hold circuit c 33 pf analog channel selector analog input pin r 6 k w comparator if the output impedance of the external circuit is high, it is recommended to connect an external capacitor of approx. 0.1 m f. . . = . . = analog input equivalent circuit
35 mb89660r series n examples characteristics v cc = 6.0 v v cc = 5.0 v v cc = 4.0 v v cc = 3.0 v 3 2 1 0 0 5 10 15 20 25 i oh2 (?a) v dd -v oh2 vs. i oh2 v dd -v oh2 (v) t a = +25 c 010 123456789 0.1 0.2 0.3 0.4 0.5 v ol (v) v cc = 3.0 v v cc = 4.0 v v cc = 5.0 v v cc = 6.0 v i ol (ma) v ol vs. i ol t a = +25 c 0.0 1.0 v cc - v oh (v) v cc = 2.5 v v cc = 3.0 v v cc = 4.0 v v cc = 5.0 v v cc = 6.0 v i oh (ma) v cc - v oh vs. i oh 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 ?.5 ?.0 ?.5 ?.0 ?.5 ?.0 t a = +25 c t a = +25 c v cc = 6.0 v v cc = 5.0 v v cc = 4.0 v v cc = 3.0 v 0.6 0.5 0.4 0.3 0.2 0.1 0 01020 i ol2 (ma) v ol2 vs. i ol2 v ol2 (v) (1) l level output voltage p00 to p07, p10 to p17,p20 to p27, p30, p32 to p36, p40 to p47, p50 to p57, p60 to p63 (2) h level output voltage p00 to p07, p10 to p17, p20 to p27, p30, p32 to p36, p40 to p47, p60 to p63 (3) l level output voltage p31, p37 (4) h level output voltage p31, p37
36 mb89660r series 012 3 456 7 v cc (v) 5.0 v in (v) v in vs. v cc 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 t a = +25 c 1 mhz 4 mhz 8 mhz 10 mhz 9 8 7 6 5 4 3 2 1 0 123456 7 123456 7 v cc (v) v cc (v) i cc (ma) i cc vs. v cc t a = +25 c i ccs (ma) i ccs vs. v cc t a = +25 c 1 mhz 4 mhz 8 mhz 10 mhz 3 2 1 0 (5) h level input voltage/l level input voltage (cmos input) (6) h level input voltage/l level input voltage (hysteresis input) (7) power supply current (external clock) 012 3 456 7 v cc (v) 5.0 v in (v) v in vs. v cc 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 v ihs v ils t a = +25 c v ihs : v ils : threshold when input voltage in hysteresis characteristics is set to ??level threshold when input voltage in hysteresis characteristics is set to ??level
37 mb89660r series r pull vs. v cc 234 5 6 r pull (k w ) 10 1 100 1000 t a = +25 c v cc (v) (8) pull-up resistance
38 mb89660r series n instructions (136 instructions) execution instructions can be divided into the following four groups: ? transfer ? arithmetic operation ? branch ?others table 1 lists symbols used for notation of instructions. table 1 instruction symbols symbol meaning dir direct address (8 bits) off offset (8 bits) ext extended address (16 bits) #vct vector table number (3 bits) #d8 immediate data (8 bits) #d16 immediate data (16 bits) dir: b bit direct address (8:3 bits) rel branch relative address (8 bits) @ register indirect (example: @a, @ix, @ep) a accumulator a (whether its length is 8 or 16 bits is determined by the instruction in use.) ah upper 8 bits of accumulator a (8 bits) al lower 8 bits of accumulator a (8 bits) t temporary accumulator t (whether its length is 8 or 16 bits is determined by the instruction in use.) th upper 8 bits of temporary accumulator t (8 bits) tl lower 8 bits of temporary accumulator t (8 bits) ix index register ix (16 bits) ep extra pointer ep (16 bits) pc program counter pc (16 bits) sp stack pointer sp (16 bits) ps program status ps (16 bits) dr accumulator a or index register ix (16 bits) ccr condition code register ccr (8 bits) rp register bank pointer rp (5 bits) ri general-purpose register ri (8 bits, i = 0 to 7) indicates that the very is the immediate data. (whether its length is 8 or 16 bits is determined by the instruction in use.) ( ) indicates that the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.) (( )) the address indicated by the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.)
39 mb89660r series columns indicate the following: mnemonic: assembler notation of an instruction ~: the number of instructions #: the number of bytes operation: operation of an instruction tl, th, ah: a content change when each of the tl, th, and ah instructions is executed. symbols in the column indicate the following: ? C indicates no change. ? dh is the 8 upper bits of operation description data. ? al and ah must become the contents of al and ah prior to the instruction executed. ? 00 becomes 00. n, z, v, c: an instruction of which the corresponding flag will change. if + is written in this column, the relevant instruction will change its corresponding flag. op code: code of an instruction. if an instruction is more than one code, it is written according to the following rule: example: 48 to 4f ? this indicates 48, 49, ... 4f.
40 mb89660r series table 2 transfer instructions (48 instructions) notes: during byte transfer to a, t ? a is restricted to low bytes. operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (reverse arrangement of f 2 mc-8 family) mnemonic ~ # operation tl th ah n z v c op code mov dir,a mov @ix +off,a mov ext,a mov @ep,a mov ri,a mov a,#d8 mov a,dir mov a,@ix +off mov a,ext mov a,@a mov a,@ep mov a,ri mov dir,#d8 mov @ix +off,#d8 mov @ep,#d8 mov ri,#d8 movw dir,a movw @ix +off,a movw ext,a movw @ep,a movw ep,a movw a,#d16 movw a,dir movw a,@ix +off movw a,ext movw a,@a movw a,@ep movw a,ep movw ep,#d16 movw ix,a movw a,ix movw sp,a movw a,sp mov @a,t movw @a,t movw ix,#d16 movw a,ps movw ps,a movw sp,#d16 swap setb dir: b clrb dir: b xch a,t xchw a,t xchw a,ep xchw a,ix xchw a,sp movw a,pc 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ? (a) ( (ix) +off ) ? (a) (ext) ? (a) ( (ep) ) ? (a) (ri) ? (a) (a) ? d8 (a) ? (dir) (a) ? ( (ix) +off) (a) ? (ext) (a) ? ( (a) ) (a) ? ( (ep) ) (a) ? (ri) (dir) ? d8 ( (ix) +off ) ? d8 ( (ep) ) ? d8 (ri) ? d8 (dir) ? (ah),(dir + 1) ? (al) ( (ix) +off) ? (ah), ( (ix) +off + 1) ? (al) (ext) ? (ah), (ext + 1) ? (al) ( (ep) ) ? (ah),( (ep) + 1) ? (al) (ep) ? (a) (a) ? d16 (ah) ? (dir), (al) ? (dir + 1) (ah) ? ( (ix) +off), (al) ? ( (ix) +off + 1) (ah) ? (ext), (al) ? (ext + 1) (ah) ? ( (a) ), (al) ? ( (a) ) + 1) (ah) ? ( (ep) ), (al) ? ( (ep) + 1) (a) ? (ep) (ep) ? d16 (ix) ? (a) (a) ? (ix) (sp) ? (a) (a) ? (sp) ( (a) ) ? (t) ( (a) ) ? (th),( (a) + 1) ? (tl) (ix) ? d16 (a) ? (ps) (ps) ? (a) (sp) ? d16 (ah) ? (al) (dir): b ? 1 (dir): b ? 0 (al) ? (tl) (a) ? (t) (a) ? (ep) (a) ? (ix) (a) ? (sp) (a) ? (pc) C C C C C al al al al al al al C C C C C C C C C al al al al al al C C C C C C C C C C C C C C C al al C C C C C C C C C C C C C C C C C C C C C C C C C ah ah ah ah ah ah C C C C C C C C C C C C C C C C ah C C C C C C C C C C C C C C C C C C C C C C C C C dh dh dh dh dh dh dh C C dh C dh C C C dh C C al C C C dh dh dh dh dh C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 45 46 61 47 48 to 4f 04 05 06 60 92 07 08 to 0f 85 86 87 88 to 8f d5 d6 d4 d7 e3 e4 c5 c6 c4 93 c7 f3 e7 e2 f2 e1 f1 82 83 e6 70 71 e5 10 a8 to af a0 to a7 42 43 f7 f6 f5 f0
41 mb89660r series table 3 arithmetic operation instructions (62 instructions) (continued) mnemonic ~ # operation tl th ah n z v c op code addc a,ri addc a,#d8 addc a,dir addc a,@ix +off addc a,@ep addcw a addc a subc a,ri subc a,#d8 subc a,dir subc a,@ix +off subc a,@ep subcw a subc a inc ri incw ep incw ix incw a dec ri decw ep decw ix decw a mulu a divu a andw a orw a xorw a cmp a cmpw a rorc a rolc a cmp a,#d8 cmp a,dir cmp a,@ep cmp a,@ix +off cmp a,ri daa das xor a xor a,#d8 xor a,dir xor a,@ep xor a,@ix +off xor a,ri and a and a,#d8 and a,dir 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 (a) ? (a) + (ri) + c (a) ? (a) + d8 + c (a) ? (a) + (dir) + c (a) ? (a) + ( (ix) +off) + c (a) ? (a) + ( (ep) ) + c (a) ? (a) + (t) + c (al) ? (al) + (tl) + c (a) ? (a) - (ri) - c (a) ? (a) - d8 - c (a) ? (a) - (dir) - c (a) ? (a) - ( (ix) +off) - c (a) ? (a) - ( (ep) ) - c (a) ? (t) - (a) - c (al) ? (tl) - (al) - c (ri) ? (ri) + 1 (ep) ? (ep) + 1 (ix) ? (ix) + 1 (a) ? (a) + 1 (ri) ? (ri) - 1 (ep) ? (ep) - 1 (ix) ? (ix) - 1 (a) ? (a) - 1 (a) ? (al) (tl) (a) ? (t) / (al),mod ? (t) (a) ? (a) (t) (a) ? (a) (t) (a) ? (a) " (t) (tl) - (al) (t) - (a) (a) - d8 (a) - (dir) (a) - ( (ep) ) (a) - ( (ix) +off) (a) - (ri) decimal adjust for addition decimal adjust for subtraction (a) ? (al) " (tl) (a) ? (al) " d8 (a) ? (al) " (dir) (a) ? (al) " ( (ep) ) (a) ? (al) " ( (ix) +off) (a) ? (al) " (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) C C C C C C C C C C C C C C C C C C C C C C C dl C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 00 C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C dh C C C C dh C C C dh dh 00 dh dh dh C C C C C C C C C C C C C C C C C C C C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + C C C C C C C C C + + C C + + + C C C C C C C C C + + C C C C C C C C C C + + r C + + r C + + r C + + + + + + + + + + C + + + C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C 28 to 2f 24 25 26 27 23 22 38 to 3f 34 35 36 37 33 32 c8 to cf c3 c2 c0 d8 to df d3 d2 d0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1f 84 94 52 54 55 57 56 58 to 5f 62 64 65 a c ? ? ?? a c
42 mb89660r series (continued) table 4 branch instructions (17 instructions) table 5 other instructions (9 instructions) mnemonic ~ # operation tl th ah n z v c op code and a,@ep and a,@ix +off and a,ri or a or a,#d8 or a,dir or a,@ep or a,@ix +off or a,ri cmp dir,#d8 cmp @ep,#d8 cmp @ix +off,#d8 cmp ri,#d8 incw sp decw sp 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (dir) C d8 ( (ep) ) C d8 ( (ix) + off) C d8 (ri) C d8 (sp) ? (sp) + 1 (sp) ? (sp) C 1 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + + + + + + + + + + + + + + + C C C C C C C C 67 66 68 to 6f 72 74 75 77 76 78 to 7f 95 97 96 98 to 9f c1 d1 mnemonic ~ # operation tl th ah n z v c op code bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel blt rel bge rel bbc dir: b,rel bbs dir: b,rel jmp @a jmp ext callv #vct call ext xchw a,pc ret reti 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 if z = 1 then pc ? pc + rel if z = 0 then pc ? pc + rel if c = 1 then pc ? pc + rel if c = 0 then pc ? pc + rel if n = 1 then pc ? pc + rel if n = 0 then pc ? pc + rel if v " n = 1 then pc ? pc + rel if v " n = 0 then pc ? pc + rei if (dir: b) = 0 then pc ? pc + rel if (dir: b) = 1 then pc ? pc + rel (pc) ? (a) (pc) ? ext vector call subroutine call (pc) ? (a),(a) ? (pc) + 1 return from subrountine return form interrupt C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + C C C + C C C C C C C C C C C C C C C C C C C C C C C C C C restore fd fc f9 f8 fb fa ff fe b0 to b7 b8 to bf e0 21 e8 to ef 31 f4 20 30 mnemonic ~ # operation tl th ah n z v c op code pushw a popw a pushw ix popw ix nop clrc setc clri seti 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r C C C s C C C C C C C C 40 50 41 51 00 81 91 80 90
43 mb89660r series n instruction map 0123456789abcdef 0 nop swap ret reti pushw a popw a mov a,ext movw a,ps clri seti clrb dir: 0 bbc dir: 0,rel incw a decw a jmp @a movw a,pc 1 mulu a divu a jmp addr16 call addr16 pushw ix popw ix mov ext,a movw ps,a clrc setc clrb dir: 1 bbc dir: 1,rel incw sp decw sp movw sp,a movw a,sp 2 rolc a cmp a addc a subc a xch a, t xor a and a or a mov @a,t mov a,@a clrb dir: 2 bbc dir: 2,rel incw ix decw ix movw ix,a movw a,ix 3 rorc a cmpw a addcw a subcw a xchw a, t xorw a andw a orw a movw @a,t movw a,@a clrb dir: 3 bbc dir: 3,rel incw ep decw ep movw ep,a movw a,ep 4 mov a,#d8 cmp a,#d8 addc a,#d8 subc a,#d8 xor a,#d8 and a,#d8 or a,#d8 daa das clrb dir: 4 bbc dir: 4,rel movw a,ext movw ext,a movw a,#d16 xchw a,pc 5 mov a,dir cmp a,dir addc a,dir subc a,dir mov dir,a xor a,dir and a,dir or a,dir mov dir,#d8 cmp dir,#d8 clrb dir: 5 bbc dir: 5,rel movw a,dir movw dir,a movw sp,#d16 xchw a,sp 6 mov a,@ix +d cmp a,@ix +d addc a,@ix +d subc a,@ix +d mov @ix +d,a xor a,@ix +d and a,@ix +d or a,@ix +d mov @ix+d,#d8 cmp @ix+d,#d8 clrb dir: 6 bbc dir: 6,rel movw a,@ix +d movw @ix +d,a movw ix,#d16 xchw a,ix 7 mov a,@ep cmp a,@ep addc a,@ep subc a,@ep mov @ep,a xor a,@ep and a,@ep or a,@ep mov @ep,#d8 cmp @ep,#d8 clrb dir: 7 bbc dir: 7,rel movw a,@ep movw @ep,a movw ep,#d16 xchw a,ep 8 mov a,r0 cmp a,r0 addc a,r0 subc a,r0 mov r0,a xor a,r0 and a,r0 or a,r0 mov r0,#d8 cmp r0,#d8 setb dir: 0 bbs dir: 0,rel inc r0 dec r0 callv #0 bnc rel 9 mov a,r1 cmp a,r1 addc a,r1 subc a,r1 mov r1,a xor a,r1 and a,r1 or a,r1 mov r1,#d8 cmp r1,#d8 setb dir: 1 bbs dir: 1,rel inc r1 dec r1 callv #1 bc rel a mov a,r2 cmp a,r2 addc a,r2 subc a,r2 mov r2,a xor a,r2 and a,r2 or a,r2 mov r2,#d8 cmp r2,#d8 setb dir: 2 bbs dir: 2,rel inc r2 dec r2 callv #2 bp rel b mov a,r3 cmp a,r3 addc a,r3 subc a,r3 mov r3,a xor a,r3 and a,r3 or a,r3 mov r3,#d8 cmp r3,#d8 setb dir: 3 bbs dir: 3,rel inc r3 dec r3 callv #3 bn rel c mov a,r4 cmp a,r4 addc a,r4 subc a,r4 mov r4,a xor a,r4 and a,r4 or a,r4 mov r4,#d8 cmp r4,#d8 setb dir: 4 bbs dir: 4,rel inc r4 dec r4 callv #4 bnz rel d mov a,r5 cmp a,r5 addc a,r5 subc a,r5 mov r5,a xor a,r5 and a,r5 or a,r5 mov r5,#d8 cmp r5,#d8 setb dir: 5 bbs dir: 5,rel inc r5 dec r5 callv #5 bz rel e mov a,r6 cmp a,r6 addc a,r6 subc a,r6 mov r6,a xor a,r6 and a,r6 or a,r6 mov r6,#d8 cmp r6,#d8 setb dir: 6 bbs dir: 6,rel inc r6 dec r6 callv #6 bge rel f mov a,r7 cmp a,r7 addc a,r7 subc a,r7 mov r7,a xor a,r7 and a,r7 or a,r7 mov r7,#d8 cmp r7,#d8 setb dir: 7 bbs dir: 7,rel inc r7 dec r7 callv #7 blt rel l h
44 mb89660r series n mask options n ordering information no. part number mb89663r mb89665r mb89p665 mb89w665 specifying procedure specify when ordering masking specify with eprom programmer 1 power-on reset power-on reset provided no power-on reset selectable selectable 2 selection of the oscillation stabilization time crystal oscillator (26.2 ms at 10 mhz) ceramic oscillator (1.64 ms at 10 mhz) selectable selectable 3 reset pin output with reset output without reset output selectable selectable 4 pull-up resistors p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p60 to p63 can be selected per pin. (pull-up resistors can not be selected for p50 to p57 when an a/d converter is used.) can be set per pin. (p54 to p57 must have the same setting) part number package remarks MB89663RP-SH mb89665rp-sh mb89p665p-sh 64-pin plastic sh-dip (dip-64p-m01) mb89663rpf mb89665rpf mb89p665pf 64-pin plastic qfp (fpt-64p-m06) mb89w665c-sh 64-pin ceramic sh-dip (dip-64c-a06)
45 mb89660r series n package dimension c 1994 fujitsu limited d64001s-3c-4 58.00 +0.22 ?.55 +.008 ?022 2.283 17.00?.25 (.669?010) index-1 5.65(.222)max 3.00(.118)min 0.51(.020)min 0.45?.10 (.018?004) +.020 ? .039 ? +0.50 1.00 1.778?.18 (.070?007) 1.778(.070) max 0.25?.05 (.010?002) 19.05(.750) typ 15?ax index-2 55.118(2.170)ref dimensions in mm (inches) 64-pin plastic sh-dip (dip-64p-m01) c 1994 fujitsu limited f64013s-3c-2 0.20(.008) m "b" 0.10(.004) 0.63(.025)max 0.18(.007)max details of "a" part 0 10 1.20?.20 details of "b" part (.047?008) 24.70?.40(.972?016) 20.00?.20(.787?008) 18.70?.40 (.736?016) 12.00(.472) ref 16.30?.40 (.642?016) 14.00?.20 (.551?008) 0.05(.002)min (stand off) 22.30?.40(.878?016) 18.00(.709)ref 0.15?.05(.006?002) 1.00(.0394) 0.40?.10 (.016?004) typ index 20 19 1 33 51 0.30(.012) 0.25(.010) 32 52 64 lead no. "a" 3.35(.132)max (mounting height) dimensions in mm (inches) 64-pin plastic qfp (fpt-64p-m06)
46 mb89660r series c 1994 fujitsu limited d64006sc-1-2 ref r1.27(.050) index area +.005 ?003 .018 ?.08 +0.13 0.46 (.0355?0040) 0.90?.10 (.070?007) 1.778?.180 max 1.45(.057) (.050?010) 1.27?.25 0.25?.05 (.010?004) 19.05?.25 (.750?010) 56.90?.56 (2.240?022) 18.75?.25 (.738?010) 55.118(2.170)ref 3.40?.36 (.134?014) typ 8.89(.350) dia 5.84(.230)max 0?9 dimensions in mm (inches) 64-pin ceramic sh-dip (dip-64c-a06)
47 mb89660r series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: 81(44) 754-3763 fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9901 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

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